1. Field of the Invention
The present disclosure relates to technology for fabricating integrated circuits such as semiconductor memory devices.
2. Description of the Related Art
The strong growth in demand for portable consumer electronics is driving the need for high-capacity storage devices. Non-volatile semiconductor memory devices, such as flash memory storage cards, are becoming widely used to meet the ever-growing demands on digital information storage and exchange. Their portability, versatility and rugged design, along with their high reliability and large capacity, have made such memory devices ideal for use in a wide variety of electronic devices, including for example digital cameras, digital music players, video game consoles, PDAs and cellular telephones. Electrically Erasable Programmable Read Only Memory (EEPROM), including flash EEPROM, and Electrically Programmable Read Only Memory (EPROM), are among the most popular non-volatile semiconductor memories.
As with most storage devices, defects occur to some of the semiconductor memory components or storage areas during fabrication. For example, the individual storage elements or memory cells of a semiconductor memory array may be defective. Additionally, the peripheral circuitry for the memory array, including word lines, bit lines, decoders, etc., may be defective, rendering the associated storage elements defective as well.
Portions of a typical semiconductor memory fabrication process are shown in the flowchart of FIG. 1. In step 20, wafer level testing is conducted prior to packaging the memory chips to form memory devices. A wafer can include hundreds or thousands of memory chips, each of which will include a memory array and peripheral components such as the control and logic circuits for accessing the memory cells of the array. During wafer level testing 20, the functionality of the memory chips is tested so that defective components are not needlessly integrated into a packaged device.
After wafer level testing 20, the wafer is divided into individual memory chips and one or more of the memory chips are mounted to a substrate, possibly along with a controller chip, and electrical connections are formed in step 22. In particular, the substrate may include a conductance pattern of photolithographically defined electrical traces. The controller and memory chips may be die bonded and electrically connected to the substrate to allow electrical communication between the controller chip and memory chips, as well as between the chip set and the outside world. After bonding and electrical connection in step 22, the die and substrate may be packaged in step 24 by encapsulating the die and substrate in a molding compound.
The packaged memory devices are then subjected to burn-in and electrical test processes in steps 26 and 28, respectively. Burn-in is performed to stress the memory arrays and peripheral circuitry of the chips. Burn-in is typically conducted at elevated temperatures (e.g., 125° C.) at which high voltages are applied at various portions of each chip to stress and identify weaker elements. Those die packages passing burn-in may undergo an electrical test in step 28. Referring to FIG. 2, during the burn-in and/or electrical test, electrical function of the package may be tested using a memory test pad matrix 32 provided within the package.
The memory test pad matrix 32 includes a plurality of electrical test pads 34 exposed through the molding compound and connected to the memory die within the package. During burn-in and/or electrical test, the package may be inserted into a socket on a test card, whereupon the test pads are contacted by probes to test the electrical properties and functioning of the semiconductor package to determine whether the finished semiconductor package performs per specification. Assuming the package passes electrical inspection, the memory test pad matrix 32 may then be covered (as for example by a sticker or ink jet printing). FIG. 2 also shows a plurality of contact fingers 36 for electrical connection of the package 30 with the outside world.
FIG. 3 is a schematic top view of a portion of a semiconductor package 30 prior to the encapsulation step. The package 30 includes a controller die 40, such as for example an ASIC, and a plurality of memory die 42, as well as the memory test pad matrix 32 discussed above. There is also shown electrical connections for carrying a chip enable signal between the controller die 40 and each of the memory die 42. As is known, during normal usage of the package 30, when read, write or erase operations (generally indicated by arrow 46) are to be performed with the memory die 42, the memory die 42 must first be enabled via a chip enable (“CE”) signal from the controller die 40 to the memory die 42. As shown, the CE signal may travel over traces 48, which are shorted together and lead to each of the memory die. Accordingly, when a CE signal is sent from the controller die 40, it is sent to each of the memory die 42 together so as to enable each of the memory die 42 even where read/write/erase operations are taking place on only one of the memory die.
In the package test phase (steps 26 and/or 28, FIG. 1), the memory die 42 are accessed directly from the memory test pad matrix 32, bypassing the controller die 40. During the test phase, when read, write or erase test operations (generally indicated by arrow 50) are to be performed with the memory die 42, the memory die must first be enabled by a CE signal sent from the memory test pad matrix 32. As shown, a trace 48 may extend from a CE signal test pad 34 in the matrix 32 and connect to the same traces 48 used to carry the CE signal from the controller. Accordingly, during test, when a CE signal is sent from the memory test pad matrix 32, it is sent to each of the memory die 42 together.
In certain semiconductor packages, there is a drive to reduce power consumption in the package. In the package 30 shown in FIG. 3, whenever a CE signal is sent, it is sent to each of the memory die 42, even though the read/write/erase operation may be occurring on a single memory die 42. Accordingly, there are power saving advantages to separating the CE signal into separate signals, one signal for each memory die in the package, so that the memory die may be individually enabled.
A problem arises however in that the same traces are used to transmit the CE signal both during electrical test and during normal operations thereafter by the controller die 40. While separate CE signals are feasible off of the controller die 40, it is difficult to provide separate CE signals from the memory test pad matrix 32 during the electrical test phase. There typically is not enough room on the test pad matrix to add enough additional pads to provide one CE signal for each memory die during test. Moreover, redesign of the memory test pad matrix would also require redesign of all of the test sockets which perform the electrical testing via the memory test pad matrix. Further still, the power saving issues which may exist during normal usage read/write/erase operations do not exist during the testing phase.
Accordingly, there is a need for a semiconductor package including a single CE signal for enabling the memory chips during the electrical test phase of the package, but which also allows for CE signals to be sent to individual memory die during normal read/write/erase operations thereafter.